1. Field
Example embodiments of the present invention relate to an etching solution, a method of forming a pattern using the same, a method of manufacturing a multiple gate oxide layer using the same and a method of manufacturing a flash memory device using the same. Other example embodiments of the present invention relate to an etching solution having an etching selectivity between a polysilicon layer and an oxide layer, a method of forming a pattern using an etching solution using the same, a method of manufacturing a multiple gate oxide layer using the same, and a method of manufacturing a flash memory device using the same.
2. Description of the Related Art
A semiconductor device may be mainly classified into two types: random access memory (RAM) and read only memory (ROM). The RAM may be a volatile memory that loses the data when the power supply is cut, but performs input and output of the data at a higher speed. Examples of the RAM are a dynamic random access memory (DRAM), a static random access memory (SRAM) and/or the like. The ROM may be a nonvolatile memory that maintains the data when the power supply is cut, but performs input and output of the data at a lower speed. Among the ROMs, an electrically erasable and programmable ROM (EEPROM) and a flash memory may have been recently used.
Flash memory may be an advanced device from the EEPROM that is electrically erasable at a higher speed. The flash memory electrically controls input and output of the data by a mechanism of Fowler-Nordheim tunneling (F-N tunneling) and/or hot electron injection. The flash memory may be generally classified into a NAND type flash memory and/or a NOR type flash memory. In the NAND type flash memory, cell transistors of n consist of a unit string and the unit string may be disposed in parallel between a bit line and a ground line. In the NOR type flash memory, each cell transistor may be disposed in parallel between a bit line and a ground line. The NAND type flash memory may be utilized for a higher-speed performance and the NOR type flash memory may be utilized for a higher integration.
In the above-mentioned device, for example, the DRAM, the SRAM, the flash memory and/or the like, a polysilicon layer pattern may be used for a gate electrode. The polysilicon layer pattern may be formed by a deposition process of polysilicon, a photolithography process, an etching process and/or any other suitable process. The etching process may be generally performed by a dry etching process using plasma. When a polysilicon layer is etched by the dry etching process using plasma, a silicon substrate below the polysilicon layer may often have etching damage caused by the plasma. In order to reduce plasma damage to the silicon substrate, the polysilicon layer may be etched by a wet etching process using an etching solution. When the polysilicon layer is etched by the wet etching process using the etching solution, an oxide layer and/or the silicon substrate may not be damaged by the etching solution.
The wet etching process using the etching solution for the polysilicon layer may be applied to a method of forming a multi tunnel oxide layer in the NOR type flash memory and/or a method of forming a floating gate layer in the NAND type flash memory. The wet etching process using the etching solution for the polysilicon layer may be applied to remove a polysilicon layer without damage to an oxide layer in a selective epitaxial growth (SEG) method.
A standard clean 1 (SC1) solution may be used as the etching solution. The SC1 solution may include ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2) and water. A volume ratio of ammonium hydroxide, hydrogen peroxide and water may be about 2.2:8.8:80. An oxide layer and a polysilicon layer may have an etching rate substantially the same when the SC1 solution is used in the wet etching process. An etching solution that has a lower etching rate for the oxide layer may be required.